The current metalization used in multilevel metal interconnections by some manufacturers include aluminum-copper lines for each level of metalization and tungsten vias or studs between conductors of respective levels of metal interconnections. The use of Cu solute additions to Al is desirable because it reduces the rate of electromigration and stress-voiding. The amount of Cu addition Al, however, is limited by the ability to reactive ion etch the Al(Cu) line to .ltoreq.2 wt. % Cu. The tungsten studs act as a complete barrier to copper and aluminum atoms which may be moved or transported at high current densities in the conductors, resulting in copper and/or aluminum depletion adjacent to tungsten studs which, in turn leads to electromigration open failures. To avoid electromigration open failures, a set of downstream ground rules for electrical current is required to limit the current densities in the conductors. The ground rules, however, limit the performance of advanced complementary metal oxide semiconductor (CMOS) logic chips. One solution to this problem is to replace the tungsten stud or via with aluminum, or some other low resistivity material through which aluminum or copper can diffuse or be transported. The main difficulties with an aluminum stud are finding a technique which can be used to fill high aspect ratio holes with aluminum to form the studs or vias. A number of methods have been investigated, such as chemical vapor deposition (CVD), electron cyclotron resonance (ECR), columnated sputtering, hot sputtering and various electro deposition techniques. With the foregoing methods, however, there are subsequent integration, throughput or thermal budget problems.
Another option is to use copper studs or vias. Filling of extremely high aspect ratio holes, greater than 3, has been recently demonstrated using plating with an (ECR) copper/tantalum liner i.e. B. Luther et al. Proceedings IEEE VLSI Multilevel Interconnections Conference, Santa Clara, California Jun. 8-9, 1993 p.15. The problem with pure copper studs or vias is that aluminum and copper react at about 250.degree. C. to form Al.sub.2 Cu with a 2.8% volume expansion. A barrier layer placed on top of the studs sufficient to prevent a reaction between the copper stud or via and the aluminum lines or conductors would also decrease the electromigration lifetime, in a similar manner as a tungsten stud or via, by preventing aluminum or copper atoms from being transported through the barrier layer in regions with high current density. Additionally, the thickness of the barrier layers on the aluminum lines or conductors would increase the line height or conductor height and hence the interlevel capacitance between adjacent conductors. If the barrier layer were to fail during subsequent processing, the copper and aluminum would react forming Al.sub.2 CU with the associated volume increase of 2.8% which would cause delamination at the metal/oxide or insulator interface.
In U.S. Pat. No. 5,010,039 which issued on Apr. 23, 1991 to S-M Ku et al., describes methods of forming contacts to a semiconductor device where via holes are etched through a deposited first insulation layer on a semiconductor chip with defined contact areas below, then sputtered, evaporated or CVD deposition of an Al/Cu alloy is performed to fill the via holes to make a contact stud. The deposited surface may then be chemical-mechanical polished to planarity.
In U.S. Pat. No. 5,071,714 which issued on Dec. 10, 1991 to K. P. Rodbell et al., a multilayered intermetallic connection for semiconductor devices is described wherein aluminum/copper alloy, less that 2% copper, is deposited on a thin layer of Ti, and another layer of Ti is subsequently deposited on top of the AlCu prior to a final cap layer of Al/Cu or Al. The layers are deposited over semiconductor contact areas and are subsequently annealed to form TiAl.sub.3 layers on both the top and bottom AlCu surfaces.
In U.S. Pat. No. 4,884,123 which issued on Nov. 28, 1989 to P. Dixit et al. entitled "Contact Plug and Interconnect Employing a Barrier Lining and a Backfilled Conductor Material", via holes are etched through a first insulator layer on a semiconductor surface over defined contact areas, and then the via interior is flashed with a thin deposit of Ti or TiN, followed by a deposition of Al/Cu, with 1% copper in alloy, to fill and form the contact plug. A second patterned metal layer may be formed contacting the formed Al/Cu contact plugs after planarization.
In U.S. Pat. No. 4,335,506 which issued on Jun. 22, 1982 to G. T. Chiu, a layer of Cu is lift-off deposited onto an Al layer, then the resist is removed and the exposed Al is etched away using the Cu layer as an etch mask. The remaining Al layer with the Cu layer above is annealed to forman Al/Cu alloy metalization and contacts. The step of annealing causes the copper to diffuse into, and alloy with the aluminum layer.